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I2S匯流排規範

I2S(Inter-IC Sound Bus)是飛利浦公司為數字音訊裝置之間的音訊資料傳輸而制定的一種匯流排標準。在飛利浦公司的I2S標準中,既規定了硬體介面規範,也規定了數字音訊資料的格式。I2S有3個主要訊號:

1、序列時鐘SCLK,也叫位時鐘BCLK,即對應數字音訊的每一位資料,SCLK有1個脈衝。SCLK的頻率=2×取樣頻率×取樣位數。

2、幀時鐘LRCK,用於切換左右聲道的資料。LRCK為“0”表示正在傳輸的是左聲道的資料,為“1”則表示正在傳輸的是右聲道的資料。LRCK的頻率等於取樣頻率。

3、序列資料SDATA,就是用二進位制補碼錶示的音訊資料。

有時為了使系統間能夠更好地同步,還需要另外傳輸一個訊號MCLK,稱為主時鐘,也叫系統時鐘(Sys Clock),是取樣頻率的256倍或384倍。

I2S格式的訊號無論有多少位有效資料,資料的最高位總是出現在LRCK變化(也就是一幀開始)後的第2個SCLK脈衝處,見下面I2S格式圖。這就使得接收端與傳送端的有效位數可以不同。如果接收端能處理的有效位數少於傳送端,可以放棄資料幀中多餘的低位資料;如果接收端能處理的有效位數多於傳送端,可以自行補足剩餘的位。這種同步機制使得數字音訊裝置的互連更加方便,而且不會造成資料錯位。

隨著技術的發展,在統一的 I2S介面下,出現了多種不同的資料格式。根據SDATA資料相對於LRCK和SCLK的位置不同,分為左對齊(較少使用)、I2S格式(即飛利浦規定的格式)和右對齊(也叫日本格式、普通格式)。

非I2S格式如圖:

I2S格式如圖:

對非I2S格式而言,為了保證數字音訊訊號的正確傳輸,傳送端和接收端應該採用相同的資料格式和長度。對I2S格式來說資料長度可以不同。而且幀時鐘LRCK高低電平對應左右聲道的意義也不同?

注意I2S匯流排和I2S格式的區別,I2S匯流排是一種匯流排標準,I2S格式是飛利浦制定的資料格式。在統一的I2S匯流排介面下,出現了左對齊和右對齊等非I2S格式。

在我們系統Android中,設定sample_rate=44.1Khz,sample_length=16,channel=2;那麼BCLK應該為2×44.1Khz×16=32xsample_rate,而實際上MCLK=11.289Mhz,BCLK=MCLK/4,sample_rate=LRCK=BLK/64=44.1Khz,BCLK和理論計算的值不符。引用“如果接收端能處理的有效位數少於傳送端,可以放棄資料幀中多餘的低位資料;如果接收端能處理的有效位數多於傳送端,可以自行補足剩餘的位”,因此這是可以解釋的。

I2S/PCM時序對比

PCM

I2S

DAI概述

增加AC97、I2S、PCM三種介面說明,摘自核心文件DAI.txt:

ASoC currently supports the three main Digital Audio Interfaces (DAI) found on
SoC controllers and portable audio CODECs today, namely AC97, I2S and PCM.
AC97
====
AC97 is a five wire interface commonly found on many PC sound cards. It is
now also popular in many portable devices. This DAI has a reset line and time
multiplexes its data on its SDATA_OUT (playback) and SDATA_IN (capture) lines.
The bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the
frame (FRAME) (usually 48kHz) is always driven by the controller. Each AC97
frame is 21uS long and is divided into 13 time slots.
The AC97 specification can be found at :-
http://www.intel.com/design/chipsets/audio/ac97_r23.pdf
I2S
===
I2S is a common 4 wire DAI used in HiFi, STB and portable devices. The Tx and
Rx lines are used for audio transmission, whilst the bit clock (BCLK) and
left/right clock (LRC) synchronise the link. I2S is flexible in that either the
controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
usually varies depending on the sample rate and the master system clock
(SYSCLK). LRCLK is the same as the sample rate. A few devices support separate
ADC and DAC LRCLKs, this allows for simultaneous capture and playback at
different sample rates.
I2S has several different operating modes:-
o I2S - MSB is transmitted on the falling edge of the first BCLK after LRC
transition.
o Left Justified - MSB is transmitted on transition of LRC.
o Right Justified - MSB is transmitted sample size BCLKs before LRC
transition.
PCM
===
PCM is another 4 wire interface, very similar to I2S, which can support a more
flexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used
to synchronise the link whilst the Tx and Rx lines are used to transmit and
receive the audio data. Bit clock usually varies depending on sample rate
whilst sync runs at the sample rate. PCM also supports Time Division
Multiplexing (TDM) in that several devices can use the bus simultaneously (this
is sometimes referred to as network mode).
Common PCM operating modes:-
o Mode A - MSB is transmitted on falling edge of first BCLK after FRAME/SYNC.
o Mode B - MSB is transmitted on rising edge of FRAME/SYNC.